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Oscillating heat pipes (OHPs) represent a promising advancement over traditional heat pipes, yet their operational boundaries, especially for long OHPs, remain insufficiently understood. This study investigates the impact of varying adiabatic length, channel diameter, and fill ratio on thermal performance, crucial for assessing their suitability for engineering applications like spacecraft thermal management. Three long OHPs, ranging from 451 mm to 770 mm in total length, were subjected to multiple performance tests, employing channel diameters of 1.1 mm and 1.9 mm, along with adiabatic lengths of 305 mm and 610 mm. The experimental setup involved mounting the OHPs onto a testbed, monitored by nine K-type thermocouples. The tests, conducted horizontally to eliminate gravity-assistance, revealed that thermal performance is significantly influenced by channel diameter, adiabatic length, and fill ratio. Notably, optimal performance was observed at a 50% fill ratio, while reductions in diameter hindered start-up at a 70% fill ratio and failed to start-up at 30% fill ratio. These findings highlight the limitations of long OHPs, which is crucial to determine the limits of their applicability and dimensional constraints. 

Domain specific computing is an idea that has been pro-posed as a path forward given the slowing of Moore’s Law and the breakdown of Dennard scaling. Two fundamental questions include: (1) how does one define a domain; and (2) how does one go about architecting hardware that performs well for that domain? We present our preliminary work towards answering these questions. 

FPGAs offer a heterogenous compute solution to the continuous de- sire for increased performance by enabling the creation of application- specific hardware that accelerates computation. While the barrier to entry has historically been steep, advances in High Level Synthe- sis (HLS) are making FPGAs more accessible. Specifically, the Intel FPGA OpenCL SDK allows software designers to abstract away low level details of architecting hardware on an FPGA and allows them to author computational kernels in a higher level language. Furthermore, Intel has developed a system that incorporates both a multicore Xeon CPU and Arria 10 FPGA into the same chip package as part of the Heterogeneous Accelerator Research Program (HARP) that can be targeted by their SDK. In this work, we target the second iteration of the HARP platform (HARPv2) using HLS through porting of OpenCL kernels originally written for FPGAs connected via a PCIe bus. We evaluate the HARPv2 system’s performance against previously reported results, explore the portability of kernels through a hardware design space search, and empirically show the benefits of using the shared virtual memory (SVM) abstraction over explicit reads and writes. 

The problem of efficiently feeding processing elements and finding ways to reduce data movement is pervasive in computing. Efficient modeling of both temporal and spatial locality of memory references is invaluable in identifying superfluous data movement in a given application. To this end, we present a new way to infer both spatial and temporal locality using reuse distance analysis. This is accomplished by performing reuse distance analysis at different data block granularities: specifically, 64B, 4KiB, and 2MiB sizes. This process of simultaneously observing reuse distance with multiple granularities is called multi-spectral reuse distance. This approach allows for a qualitative analysis of spatial locality, through observing the shifting of mass in an application's reuse signature at different granularities. Furthermore, the shift of mass is empirically measured by calculating the Earth Mover's Distance between reuse signatures of an application. From the characterization, it is possible to determine how spatially dense the memory references of an application are based on the degree to which the mass has shifted (or not shifted) and how close (or far) the Earth Mover's Distance is to zero as the data block granularity is increased. It is also possible to determine an appropriate page size from this information, and whether or not a given page is being fully utilized. From the applications profiled, it is observed that not all applications will benefit from having a larger page size. Additionally, larger data block granularities subsuming smaller ones suggest that larger pages will allow for more spatial locality exploitation, but examining the memory footprint will show whether those larger pages are fully utilized or not.